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? 1996-2013 microchip technology inc. ds30445d-page 1 high performance risc cpu features: ? only 35 single word instructions to learn ? all instructions single cycle (400 ns @ 10 mhz) except for program branches which are two-cycle ? operating speed: dc - 10 mhz clock input dc - 400 ns instruction cycle ? 14-bit wide instructions ? 8-bit wide data path ? 1k x 14 eeprom program memory ? 36 x 8 general purpose registers (sram) ? 64 x 8 on-chip eeprom data memory ? 15 special function hardware registers ? eight-level deep hardware stack ? direct, indirect and relative addressing modes ? four interrupt sources: - external rb0/int pin - tmr0 timer overflow - portb<7:4> interrupt on change - data eeprom write complete ? 1,000,000 data memory eeprom erase/write cycles ? eeprom data retention > 40 years peripheral features: ? 13 i/o pins with individual direction control ? high current sink/source for direct led drive - 25 ma sink max. per pin - 20 ma source max. per pin ? tmr0: 8-bit timer/counter with 8-bit programmable prescaler special microcontroller features: ? power-on reset (por) ? power-up timer (pwrt) ? oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? code protection ? power saving sleep mode ? selectable oscillator options ? serial in-system programming - via two pins pin diagram cmos technology: ? low-power, high-speed cmos eeprom technology ? fully static design ? wide operating voltage range: - commercial: 2.0v to 6.0v - industrial: 2.0v to 6.0v ? low power consumption: - < 2 ma typical @ 5v, 4 mhz -60 ? a typical @ 2v, 32 khz -26 ? a typical standby current @ 2v ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ra2 ra3 ra4/t0cki mclr v ss rb0/int rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c84 pdip, soic pic16c84 8-bit cmos eeprom microcontroller
pic16c84 ds30445d-page 2 ? 1996-2013 microchip technology inc. table of contents 1.0 general description ......................................................................................................... .............................................................. 3 2.0 pic16c84 device varieties ................................................................................................... ........................................................ 5 3.0 architectural overview ...................................................................................................... ............................................................. 7 4.0 memory organization......................................................................................................... .......................................................... 11 5.0 i/o ports ................................................................................................................... .................................................................... 19 6.0 timer0 module and tmr0 register ............................................................................................. ................................................ 25 7.0 data eeprom memory.......................................................................................................... ..................................................... 31 8.0 special features of the cpu ................................................................................................. ...................................................... 35 9.0 instruction set summary..................................................................................................... ......................................................... 51 10.0 development support ........................................................................................................ .......................................................... 67 11.0 electrical characteristics for pic16c84 .................................................................................... ................................................... 71 12.0 dc & ac characteristics graphs/tables for pic16c84 ......................................................................... ..................................... 83 13.0 packaging information ...................................................................................................... ........................................................... 97 appendix a: feature improvements - from pic16c5x to pic16c84 .................................................................... ........................ 99 appendix b: code compatibility - from pic16c5x to pic16c84..................................................................... ............................... 99 appendix c: what?s new in this data sheet ....................................................................................... .......................................... 100 appendix d: what?s changed in this data sheet ................................................................................... ...................................... 100 appendix e: conversion considerations - pic16c84 to pic16f83/f84 and pic16cr83/cr84............................................. ..... 101 index .......................................................................................................................... ........................................................................ 103 on-line support................................................................................................................ ................................................................. 105 pic16c84 product identification system ......................................................................................... .................................................. 107 sales and support.............................................................................................................. ................................................................ 107 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 3 1.0 general description the pic16c84 is a low-cost, high-performance, cmos, fully-static, 8-bit microcontroller. all pic16/17 microcontrollers employ an advanced risc architecture. pic16cxx devices have enhanced core features, eight-level deep stack, and multiple inter- nal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). a total of 35 instructions (reduced instruction set) are available. additionally, a large register set is used to achieve a very high performance level. pic16cxx microcontrollers typically achieve a 2:1 code compression and up to a 2:1 speed improvement (at 10 mhz) over other 8-bit microcontrollers in their class. the pic16c84 has 36 bytes of ram, 64 bytes of data eeprom memory, and 13 i/o pins. a timer/counter is also available. the pic16cxx family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) mode offers power savings. the user can wake the chip from sleep through several external and internal interrupts and resets. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software lock- up. the pic16c84 eeprom program memory allows the same device package to be used for prototyping and production. in-circuit reprogrammability allows the code to be updated without the device being removed from the end application. this is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. this is also useful for remote applications where the code may need to be updated (such as rate information). table 1-1 lists the features of the pic16c84. a simpli- fied block diagram of the pic16c84 is shown in figure 3-1. the pic16c84 fits perfectly in applications ranging from high speed automotive and appliance motor control to low-power remote sensors, electronic locks, security devices and smart cards. the eeprom technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, security codes, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applications with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16c84 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, pwm functions and co-processor applications). the serial in-system programming feature (via two pins) offers flexibility of customizing the product after complete assembly and testing. this feature can be used to serialize a product, store calibration data, or program the device with the current firmware before shipping. 1.1 family and upward compatibility those users familiar with the pic16c5x family of microcontrollers will realize that this is an enhanced version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for pic16c5x can be easily ported to the pic16c84 (appendix b). 1.2 development support the pic16cxx family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. a ?c? compiler and fuzzy logic support tools are also available.
pic16c84 ds30445d-page 4 ? 1996-2013 microchip technology inc. table 1-1 pic16c8x family of devices pic16f83 pic16cr83 pic16f84 pic16cr84 clock maximum frequency of operation (mhz) 10 10 10 10 flash program memory 512 ? 1k ? memory eeprom program memory ? ? ? ? rom program memory ? 512 ? 1k data memory (bytes) 36 36 68 68 data eeprom (bytes) 64 64 64 64 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 features interrupt sources 4 4 4 4 i/o pins 13 13 13 13 voltage range (volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 packages 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic all pic ? family devices have power-on reset, selectable watchdog ti mer, selectable code protect and high i/o current capability. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 5 2.0 pic16c84 device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements the proper device option can be selected using the information in this section. when placing orders, please use the ?pic16c84 product identification system? at the back of this data sheet to specify the correct part number. there are two device ?types? as indicated in the device number. 1. c , as in pic16 c 84. these devices have eeprom program memory and operate over the standard voltage range. 2. lc , as in pic16 lc 84. these devices have eeprom program memory and operate over an extended voltage range. when discussing memory maps and other architectural features, the use of c also implies the lc versions. 2.1 electrically erasable devices these devices are offered in the lower cost plastic package, even though the device can be erased and reprogrammed. this allows the same device to be used for prototype development and pilot programs as well as production. a further advantage of the electrically erasable version is that they can be erased and reprogrammed in-circuit, or by device programmers, such as microchip's picstart ? plus or pro mate ? ii programmers.
pic16c84 ds30445d-page 6 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 7 3.0 architectural overview the high performance of the pic16cxx family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16cxx uses a harvard architecture. this architecture has the program and data accessed from separate memories. so the device has a program memory bus and a data memory bus. this improves bandwidth over traditional von neumann architecture where program and data are fetched from the same memory (accesses over the same bus). separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. pic16cxx opcodes are 14-bits wide, enabling single word instructions. the full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions (example 3-1). consequently, all instructions exe- cute in a single cycle (400 ns @ 10 mhz) except for program branches. the pic16c84 addresses 1k x 14 program memory. all program memory is internal. pic16cxx devices can directly or indirectly address its register files or data memory. all special function registers including the program counter are mapped in the data memory. an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic16cxx simple yet efficient. in addition, the learning curve is reduced significantly. the pic16c84 has 36 x 8 sram and 64 x 8 eeprom data memory.
pic16c84 ds30445d-page 8 ? 1996-2013 microchip technology inc. pic16cxx devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the working register (w register), and the other operand is a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. a simplified block diagram for the pic16c84 is shown in figure 3-1, its corresponding pin description is shown in table 3-1. figure 3-1: pic16c84 block diagram eeprom program memory program counter 13 program bus 14 instruction reg 8 level stack (13-bit) direct addr 8 instruction decode & control timing generation osc2/clkout osc1/clkin power-up timer oscillator start-up timer power-on reset watchdog timer mclr v dd , v ss w reg alu mux i/o ports tmr0 status reg fsr reg indirect addr ra3:ra0 rb7:rb1 ra4/t0cki eeadr eeprom data memory 64 x 8 eedata addr mux ram addr ram file registers eeprom data memory data bus 8 5 7 7 1k x 14 36 x 8 rb0/int
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 9 table 3-1 pic16c8x pinout description pin name dip no. soic no. i/o/p type buffer type description osc1/clkin 16 16 i st/cmos (1) oscillator crystal input/external clock source input. osc2/clkout 15 15 o ? oscillator crystal output. connects to crystal or resonator in crys- tal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0 17 17 i/o ttl ra1 18 18 i/o ttl ra2 1 1 i/o ttl ra3 2 2 i/o ttl ra4/t0cki 3 3 i/o st can also be selected to be the clock input to the tmr0 timer/ counter. output is open drain type. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 6 6 i/o ttl rb0/int can also be selected as an external interrupt pin. rb1 7 7 i/o ttl rb2 8 8 i/o ttl rb3 9 9 i/o ttl rb4 10 10 i/o ttl interrupt on change pin. rb5 11 11 i/o ttl interrupt on change pin. rb6 12 12 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 13 13 i/o ttl/st (2) interrupt on change pin. serial programming data. v ss 5 5 p ? ground reference for logic and i/o pins. v dd 14 14 p ? positive supply for logic and i/o pins. legend: i= input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 2: this buffer is a schmitt trigger input when used in serial programming mode.
pic16c84 ds30445d-page 10 ? 1996-2013 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2. 3.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register? in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 11 4.0 memory organization there are two memory blocks in the pic16c84. these are the program memory and the data memory. each block has its own bus, so that access to each block can occur during the same oscillator cycle. the data memory can further be broken down into the general purpose ram and the special function registers (sfrs). the operation of the sfrs that control the ?core? are described here. the sfrs used to control the peripheral modules are described in the section discussing each individual peripheral module. the data memory area also contains the data eeprom memory. this memory is not directly mapped into the data memory, but is indirectly mapped. that is an indirect address pointer specifies the address of the data eeprom memory to read/write. the 64 bytes of data eeprom memory have the address range 0h-3fh. more details on the eeprom memory can be found in section 7.0. 4.1 program memory organization the pic16cxx has a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the pic16c84, only the first 1k x 14 (0000h-03ffh) are physically implemented (figure 4-1). accessing a loca- tion above the physically implemented address will cause a wraparound. for example, locations 20h, 420h, 820h, c20h, 1020h, 1420h, 1820h, and 1c20h will be the same instruction. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: program memory map and stack pc<12:0> stack level 1 ? stack level 8 reset vector peripheral interrupt vector ? ? user memory space call, return retfie, retlw 13 0000h 0004h 1fffh 3ffh
pic16c84 ds30445d-page 12 ? 1996-2013 microchip technology inc. 4.2 data memory organization the data memory is partitioned into two areas. the first is the special function registers (sfr) area, while the second is the general purpose registers (gpr) area. the sfrs control the operation of the device. portions of data memory are banked. this is for both the sfr area and the gpr area. the gpr area is banked to allow greater than 116 bytes of general purpose ram. the banked areas of the sfr are for the registers that control the peripheral functions. banking requires the use of control bits for bank selection. these control bits are located in the status register. figure 4-2 shows the data memory map organization. instructions movwf and movf can move values from the w register to any location in the register file (?f?), and vice-versa. the entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the file select register (fsr) (section 4.5). indirect addressing uses the present value of the rp1:rp0 bits for access into the banked areas of data memory. data memory is partitioned into two banks which contain the general purpose registers and the special function registers. bank 0 is selected by clearing the rp0 bit (status<5>). setting the rp0 bit selects bank 1. each bank extends up to 7fh (128 bytes). the first twelve locations of each bank are reserved for the special function registers. the remainder are gen- eral purpose registers implemented as static ram. 4.2.1 general purpose register file all devices have some amount of general purpose register (gpr) area. each gpr is 8 bits wide and is accessed either directly or indirectly through the fsr (section 4.5). the gpr addresses in bank 1 are mapped to addresses in bank 0. as an example, addressing loca- tion 0ch or 8ch will access the same gpr. 4.2.2 special function registers the special function registers (figure 4-2 and table 4-1) are used by the cpu and peripheral functions to control the device operation. these registers are static ram. the special function registers can be classified into two sets, core and peripheral. those associated with the core functions are described in this section. those related to the operation of the peripheral features are described in the section for that specific feature. figure 4-2: register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 2fh 30h 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch ffh bank 0 bank 1 indirect addr. (1) indirect addr. (1) tmr0 option pcl status fsr porta portb eedata eeadr pclath intcon 36 general purpose registers (sram) pcl status fsr trisa trisb eecon1 eecon2 (1) pclath intcon mapped in bank 0 unimplemented data memory location; read as '0'. file address afh b0h note 1: not a physical register. (accesses)
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 13 table 4-1 register file summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (note3) bank 0 00h indf uses contents of fsr to address data memory (not a physical register) ---- ---- ---- ---- 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h pcl low order 8 bits of the program counter (pc) 0000 0000 0000 0000 03h status (2) irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 05h porta ? ? ? ra4/t0cki ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int xxxx xxxx uuuu uuuu 07h unimplemented location, read as '0' ---- ---- ---- ---- 08h eedata eeprom data register xxxx xxxx uuuu uuuu 09h eeadr eeprom address register xxxx xxxx uuuu uuuu 0ah pclath ? ? ? write buffer for upper 5 bits of the pc (1) ---0 0000 ---0 0000 0bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u bank 1 80h indf uses contents of fsr to address data memory (not a physical register) ---- ---- ---- ---- 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl low order 8 bits of program counter (pc) 0000 0000 0000 0000 83h status (2) irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h fsr indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 85h trisa ? ? ? porta data direction register ---1 1111 ---1 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h unimplemented location, read as '0' ---- ---- ---- ---- 88h eecon1 ? ? ? eeif wrerr wren wr rd ---0 x000 ---0 q000 89h eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- 0ah pclath ? ? ? write buffer for upper 5 bits of the pc (1) ---0 0000 ---0 0000 0bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. note 1: the upper byte of the program counter is not directly accessi ble. pclath is a slave register for pc<12:8>. the contents of pclath can be transferred to the upper byte of the program counter, but the contents of pc<12:8> is never transferred to pclath. 2: the to and pd status bits in the status register are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic16c84 ds30445d-page 14 ? 1996-2013 microchip technology inc. 4.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bit for data memory. as with any register, the status register can be the destination for any instruction. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). only the bcf, bsf, swapf and movwf instructions should be used to alter the status register (table 9-2) because these instructions do not affect any status bit. figure 4-3: status register (address 03h, 83h) note 1: the irp and rp1 bits (status<7:6>) are not used by the pic16c84 and should be programmed as cleared. use of these bits as general purpose r/w bits is not recommended, since this may affect upward compatibility with future products. note 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. note 3: when the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. the specified bit(s) will be updated according to device logic r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 0 = bank 0, 1 (00h - ffh) 1 = bank 2, 3 (100h - 1ffh) the irp bit is not used by the pic16c8x. irp should be maintained clear. bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 00 = bank 0 (00h - 7fh) 01 = bank 1 (80h - ffh) 10 = bank 2 (100h - 17fh) 11 = bank 3 (180h - 1ffh) each bank is 128 bytes. only bit rp0 is used by the pic16c8x. rp1 should be maintained clear. bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and addlw instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit (for addwf and addlw instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 15 4.2.2.2 option_reg register the option_reg register is a readable and writable register which contains various control bits to configure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. figure 4-4: option_reg register (address 81h) note: when the prescaler is assigned to the wdt (psa = '1'), tmr0 has a 1:1 prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled (by individual port latch values) bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to tmr0 bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c84 ds30445d-page 16 ? 1996-2013 microchip technology inc. 4.2.2.3 intcon register the intcon register is a readable and writable register which contains the various enable bits for all interrupt sources. figure 4-5: intcon register (address 0bh, 8bh) note: interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie eeie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts note: for the operation of the interrupt structure, please refer to section 8.5. bit 6: eeie : ee write complete interrupt enable bit 1 = enables the ee write complete interrupt 0 = disables the ee write complete interrupt bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int interrupt enable bit 1 = enables the rb0/int interrupt 0 = disables the rb0/int interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 has overflowed (must be cleared in software) 0 = tmr0 did not overflow bit 1: intf : rb0/int interrupt flag bit 1 = the rb0/int interrupt occurred 0 = the rb0/int interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 17 4.3 program counter: pcl and pclath the program counter (pc) is 13-bits wide. the low byte is the pcl register, which is a readable and writable register. the high byte of the pc (pc<12:8>) is not directly readable nor writable and comes from the pclath register. the pclath (pc latch high) register is a holding register for pc<12:8>. the contents of pclath are transferred to the upper byte of the program counter when the pc is loaded with a new value. this occurs during a call, goto or a write to pcl. the high bits of pc are loaded from pclath as shown in figure 4-6. figure 4-6: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 word block). refer to the application note ?implementing a table read? (an556). 4.3.2 program memory paging the pic16c84 has 1k of program memory. the call and goto instructions have an 11-bit address range. this 11-bit address range allows a branch within a 2k program memory page size. for future pic16cxx program memory expansion, there must be another two bits to specify the program memory page. these paging bits come from the pclath<4:3> bits (figure 4-6). when doing a call or a goto instruction, the user must ensure that these page bits (pclath<4:3>) are programmed to the desired program memory page. if a call instruction (or interrupt) is executed, the entire 13-bit pc is ?pushed? onto the stack (see next section). therefore, manipula- tion of the pclath<4:3> is not required for the return instructions (which ?pops? the pc from the stack). 4.4 s tack the pic16c84 has an 8 deep x 13-bit wide hardware stack (figure 4-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the entire 13-bit pc is ?pushed? onto the stack when a call instruction is executed or an interrupt is acknowl- edged. the stack is ?popped? in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or a pop operation. the stack operates as a circular buffer. that is, after the stack has been pushed eight times, the ninth push over- writes the value that was stored from the first push. the tenth push overwrites the second push (and so on). if the stack is effectively popped nine times, the pc value is the same as the value from the first pop. pc 12 8 7 0 5 pclath<4:0> pclath inst with pcl a s dest alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl note: the pic16c84 ignores the pclath<4:3> bits, which are used for program memory pages 1, 2 and 3 (0800h - 1fffh). the use of pclath<4:3> as general purpose r/w bits is not recommended since this may affect upward compatibility with future products. note: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instructions, or the vectoring to an interrupt address. note: there are no status bits to indicate stack overflow or stack underflow conditions.
pic16c84 ds30445d-page 18 ? 1996-2013 microchip technology inc. 4.5 indirect addressing; indf and fsr registers the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing ? register file 05 contains the value 10h ? register file 06 contains the value 0ah ? load the value 05 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 06) ? a read of the indf register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue figure 4-7: direct/indirect addressing direct addressing rp1 rp0 6 from opcode 0 irp 7 (fsr) 0 indirect addressing bank select location select bank select location select 00 01 10 11 00h 7fh 00h 0bh 0ch 2fh 30h 7fh not used bank 0 bank 1 bank 2 bank 3 addresses map back to bank 0 data memory not used
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 19 5.0 i/o ports the pic16c84 has two ports, porta and portb. some port pins are multiplexed with an alternate func- tion for other features on the device. 5.1 porta and trisa registers porta is a 5-bit wide latch. ra4 is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. all pins have data direction bits (tris registers) which can configure these pins as output or input. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, i.e., put the contents of the output latch on the selected pin. reading the porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. the ra4 pin is multiplexed with the tmr0 clock input. figure 5-1: block diagram of pins ra3:ra0 example 5-1: initializing porta clrf porta ; initialize porta by ; setting output ; data latches bsf status, rp0 ; select bank 1 movlw 0x0f ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra4 as outputs ; trisa<7:5> are always ; read as '0'. figure 5-2: block diagram of pin ra4 note: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port ttl input buffer v ss v dd i/o pin note: for crystal oscillator configurations operating below 500 khz, the device may generate a spurious internal q-clock when porta<0> switches state. this does not occur with an external clock in rc mode. to avoid this, the ra0 pin should be kept static, i.e. in input/output mode, pin ra0 should not be toggled. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss ra4 pin tmr0 clock input note: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en
pic16c84 ds30445d-page 20 ? 1996-2013 microchip technology inc. table 5-1 porta functions table 5-2 summary of registers associated with porta name bit0 buffer type function ra0 bit0 ttl input/output ra1 bit1 ttl input/output ra2 bit2 ttl input/output ra3 bit3 ttl input/output ra4/t0cki bit4 st input/output or external clock input for tmr0. output is open drain type. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 05h porta ? ? ? ra4/t0cki ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are unimplemented, read as '0'
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 21 5.2 portb and trisb registers portb is an 8-bit wide bi-directional port. the corresponding data direction register is trisb. a '1' on any bit in the trisb register puts the corresponding output driver in a hi-impedance mode. a '0' on any bit in the trisb register puts the contents of the output latch on the selected pin(s). each of the portb pins have a weak internal pull-up. a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (option_reg<7>) bit. the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of portb?s pins, rb7:rb4, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt on change comparison). the pins value in input mode are compared with the old value latched on the last read of portb. the ?mismatch? outputs of the pins are or?ed together to generate the rb port change interrupt. figure 5-3: block diagram of pins rb7:rb4 this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) read (or write) portb. this will end the mis- match condition. b) clear flag bit rbif. a mismatch condition will continue to set the rbif bit. reading portb will end the mismatch condition, and allow the rbif bit to be cleared. this interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression (see an552 in the embedded control handbook). the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 5-4: block diagram of pins rb3:rb0 data latch from other rbpu (1) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer note 1: trisb = '1' enables weak pull-up (if rbpu = '0' in the option_reg register). 2: i/o pins have diode protection to v dd and v ss . pin (2) note 1: if a change on the i/o pin should occur when a read operation of portb is being executed (start of the q2 cycle), the rbif interrupt flag bit may not be set. rbpu (1) note 1: trisb = '1' enables weak pull-up (if rbpu = '0' in the option_reg register). 2: i/o pins have diode protection to v dd and v ss . data latch p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int tris latch ttl input buffer i/o pin (2)
pic16c84 ds30445d-page 22 ? 1996-2013 microchip technology inc. example 5-1: initializing portb clrf portb ; initialize portb by ; setting output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs table 5-3 portb functions table 5-4 summary of registers associated with portb name bit buffer type i/o consistency function rb0/int bit0 ttl input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programma- ble weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programma- ble weak pull-up. rb6 bit6 ttl/st (1) input/output pin (with interrupt on change). internal software programma- ble weak pull-up. serial programming clock. rb7 bit7 ttl/st (1) input/output pin (with interrupt on change). internal software programma- ble weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger. note 1: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 23 5.3 i/o programming considerations 5.3.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs defined. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch is unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (i.e., bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?wired-or?, ?wired-and?). the resulting high output current may damage the chip. 5.3.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5- 5). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such that the pin voltage stabilizes (load dependent) before the next instruction which causes that file to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instruc- tions with a nop or another instruction not accessing this i/o port. example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. example 5-1: read-modify-write instructions on an i/o port ;initial port settings: portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp ppp 11pp ppp bcf portb, 6 ; 10pp ppp 11pp ppp bsf status, rp0 ; bcf trisb, 7 ; 10pp ppp 11pp ppp bcf trisb, 6 ; 10pp ppp 10pp ppp ; ;note that the user may have expected the ;pin values to be 00pp ppp. the 2nd bcf ;caused rb7 to be latched as the pin value ;(high). figure 5-5: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w pc t pd note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25t cy - t pd ) where t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be prob- lematic.
pic16c84 ds30445d-page 24 ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. ds30445d-page 25 pic16c84 6.0 timer0 module and tmr0 register the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module (figure 6-1) will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode tmr0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the t0 source edge select bit, t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.2. the prescaler is shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled, in software, by control bit psa (option<3>). clearing bit psa will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler (section 6.3) is assigned to the timer0 module, the prescale value (1:2, 1:4, ..., 1:256) is software selectable. 6.1 tmr0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h. this overflow sets the t0if bit (intcon<2>). the interrupt can be masked by clearing enable bit t0ie (intcon<5>). the t0if bit must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt (figure 6-4) cannot wake the processor from sleep since the timer is shut off during sleep. figure 6-1: tmr0 block diagram figure 6-2: tmr0 timing: inte rnal clock/no prescaler note 1: bits t0cs, t0se, ps2, ps1, ps0 and psa are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-6) ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 register psout (2 cycle delay) psout data bus 8 set bit t0if on overflow psa ps2, ps1, ps0 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed
pic16c84 ds30445d-page 26 ? 1996-2013 microchip technology inc. figure 6-3: tmr0 timing: inte rnal clock/prescale 1:2 figure 6-4: tmr0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) tmr0 timer t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction flow pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: t0if interrupt flag is sampled here (every q1). 2: interrupt latency = 3.25tcy, where tcy = instruction cycle time. 3: clkout is available only in rc oscillator mode. 4 interrupt latency (2) 4: the timer clock (after the synchronizer circuit) which increments the timer from ffh to 00h immediately sets the t0if bit. the tmr0 register will roll over 3 tosc cycles later.
? 1996-2013 microchip technology inc. ds30445d-page 27 pic16c84 6.2 using tmr0 with external clock when an external clock input is used for tmr0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of the tmr0 register after synchronization. 6.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of pin ra4/t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2tosc (plus a small rc delay) and low for at least 2tosc (plus a small rc delay). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4tosc (plus a small rc delay) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the ac electrical specifications of the desired device. 6.2.2 tmr0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. 6.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (figure 6-6). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. note that there is only one prescaler available which is mutually exclusive between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the timer0 module (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. figure 6-5: timer0 timing with external clock increment tmr0 (q4) ext. clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 tmr0 t0 t0 + 1 t0 + 2 ext. clock/prescaler output after sampling (note 3) note 1: 2: 3: delay from clock input change to tmr0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on tmr0 input = ? 4tosc max. external clock if no prescaler selected, prescaler output otherwise. the arrows ? indicate where sampling occurs. a small clock pulse may be missed by sampling. prescaler out (note 2)
pic16c84 ds30445d-page 28 ? 1996-2013 microchip technology inc. figure 6-6: block diagram of the tmr0/wdt prescaler ra4/t0cki t0se pin m u x clkout (= fosc/4) sync 2 cycles tmr0 register 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are bits in the option register. psa wdt enable bit m u x 0 1 0 1 data bus set bit t0if on overflow 8 psa t0cs
? 1996-2013 microchip technology inc. ds30445d-page 29 pic16c84 6.3.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on the fly? during program execution). note: to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be taken even if the wdt is disabled. to change prescaler from the wdt to the timer0 module use the sequence shown in example 6-2. example 6-1: changing prescaler (timer0 ? wdt) bcf status, rp0 ;bank 0 clrf tmr0 ;clear tmr0 ; and prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b'xxxx1xxx' ;select new movwf option ; prescale value bcf status, rp0 ;bank 0 example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ; prescaler bsf status, rp0 ;bank 1 movlw b'xxxx0xxx' ;select tmr0, new ; prescale value ? and clock source movwf option ; bcf status, rp0 ;bank 0 table 6-1 registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 0bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unknown, u = unchanged. - = unimplemented read as '0'. shaded cells are not associated with timer0.
pic16c84 ds30445d-page 30 ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. ds30445d-page 31 pic16c84 7.0 data eeprom memory the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory. these registers are: ? eecon1 ? eecon2 ? eedata ? eeadr eedata holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. pic16c84 devices have 64 bytes of data eeprom with an address range from 0h to 3fh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write- time will vary with voltage and temperature as well as from chip to chip. please refer to ac specifications for exact limits. when the device is code protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access this memory. 7.1 eeadr the eeadr register can address up to a maximum of 256 bytes of data eeprom. only the first 64 bytes of data eeprom are implemented. the upper two bits are address decoded. this means that these two bits must always be '0' to ensure that the address is in the 64 byte memory space. figure 7-1: eecon1 register (address 88h) u u u r/w-0 r/w-x r/w-0 r/s-0 r/s-x ? ? ? eeif wrerr wren wr rd r = readable bit w = writable bit s = settable bit u = unimplemented bit, read as ?0? - n = value at por reset bit7 bit0 bit 7:5 unimplemented: read as '0' bit 4 eeif : eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 wrerr : eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren : eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr : write control bit 1 = initiates a write cycle. (the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software. 0 = write cycle to the data eeprom is complete bit 0 rd : read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software). 0 = does not initiate an eeprom read
pic16c84 ds30445d-page 32 ? 1996-2013 microchip technology inc. 7.2 eecon1 and eecon2 registers eecon1 is the control register with five low order bits physically implemented. the upper-three bits are non- existent and read as '0's. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the data and address will be unchanged in the eedata and eeadr registers. interrupt flag bit eeif is set when write is complete. it must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all '0's. the eecon2 register is used exclusively in the data eeprom write sequence. 7.3 reading the eeprom data memory to read a data memory location, the user must write the address to the eeadr register and then set control bit rd (eecon1<0>). the data is available, in the very next cycle, in the eedata register; therefore it can be read in the next instruction. eedata will hold this value until another read or until it is written to by the user (during a write operation). example 7-1: data eeprom read bcf status, rp0 ; bank 0 movlw config_addr ; movwf eeadr ; address to read bsf status, rp0 ; bank 1 bsf eecon1, rd ; ee read bcf status, rp0 ; bank 0 movf eedata, w ; w = eedata 7.4 writing to the eeprom data memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedata register. then the user must follow a specific sequence to initiate the write for each byte. example 7-1: data eeprom write bsf status, rp0 ; bank 1 bcf intcon, gie ; disable ints. bsf eecon1, wren ; enable write movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit ; begin write bsf intcon, gie ; enable ints. the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. note: the data eeprom memory e/w cycle time may occasionally exceed the 10 ms specification (typical). to ensure that the write cycle is complete, use the ee interrupt or poll the wr bit (eecon1<1>). both these events signify the completion of the write cycle. required sequence
? 1996-2013 microchip technology inc. ds30445d-page 33 pic16c84 7.5 write verify depending on the application, good programming prac- tice may dictate that the value written to the data eeprom should be verified (example 7-1) to the desired value to be written. this should be used in applications where an eeprom bit will be stressed near the specification limit. the total endurance disk will help determine your comfort level. generally the eeprom write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the bit). example 7-1: write verify bcf status, rp0 ; bank 0 : ; any code can go here : ; movf eedata, w ; must be in bank 0 bsf status, rp0 ; bank 1 read bsf eecon1, rd ; yes, read the ; value written bcf status, rp0 ; bank 0 ; ; is the value written (in w reg) and ; read (in eedata) the same? ; subwf eedata, w ; btfss status, z ; is difference 0? goto write_err ; no, write error : ; yes, good write : ; continue program 7.6 protection against spurious write s there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. 7.7 data eeprom operation during code protect when the device is code protected, the cpu is able to read and write unscrambled data to the data eeprom. for rom devices, there are two code protection bits (section 8.1). one for the rom program memory and one for the data eeprom memory. 7.8 power consumption considerations note: it is recommended that the eeadr<7:6> bits be cleared. when either of these bits is set, the maximum i dd for the device is higher than when both are cleared. the specification is 400 ? a. with eeadr<7:6> cleared, the maximum is approximately 150 ? a. table 7-1 registers/bits associated with data eeprom address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 08h eedata eeprom data register xxxx xxxx uuuu uuuu 09h eeadr eeprom address register xxxx xxxx uuuu uuuu 88h eecon1 ? ? ? eeif wrerr wren wr rd ---0 x000 ---0 q000 89h eecon2 eeprom control register 2 ---- ---- ---- ---- legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. shaded cells are not used by data eeprom.
pic16c84 ds30445d-page 34 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 35 8.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. the pic16c84 has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: ?osc selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming the pic16c84 has a watchdog timer which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only. this design keeps the device in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode offers a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer time-out or through an interrupt. several oscillator options are provided to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select the various options. 8.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in program memory location 2007h. address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3fffh). this space can only be accessed during programming. to find out how to program the pic16c84, refer to pic16c84 eeprom memory programming specifica- tion (ds30189). figure 8-1: configurat ion word u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 r/p-u r/p-u r/p-u r/p-u r/p-u ? ? ? ? ? ? ? ? ? cp pwrte wdte fosc1 fosc0 bit13 bit0 r = readable bit p = programmable bit u = unimplemented bit, read as ?1? - n = value at por reset u = unchanged bit 13:5 unimplemented: read as '1' bit 4 cp : code protection bit 1 = code protection off 0 = all memory is code protected bit 3 pwrte : power-up timer enable bit 1 = power-up timer is enabled 0 = power-up timer is disabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1:0 fosc1:fosc0 : oscillator selection bits 11 =rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator
pic16c84 ds30445d-page 36 ? 1996-2013 microchip technology inc. 8.2 oscillator configurations 8.2.1 oscillator types the pic16c84 can be operated in four different oscillator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 8.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 8-2). figure 8-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) the pic16c84 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/ clkin pin (figure 8-3). figure 8-3: external clock input operation (hs, xt or lp osc configuration) table 8-1 capacitor selection for ceramic resonators table 8-2 capacitor selection for crystal oscillator note1: see table 8-1 and table 8-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16cxx rs (2) internal osc1 osc2 open clock from ext. system pic16cxx ranges tested: mode freq osc1/c1 osc2/c2 xt 455 khz 2.0 mhz 4.0 mhz 47 - 100 pf 15 - 33 pf 15 - 33 pf 47 - 100 pf 15 - 33 pf 15 - 33 pf hs 8.0 mhz 10.0 mhz 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : recommended values of c1 and c2 are identical to the ranges tested table. higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for des ign guidance only. since each resonator has its own c haracteristics, the user should consult the resonator manufacturer for the appropriate values of external components. resonators tested: 455 khz panasonic efo-a455k04b ?? 0.3% 2.0 mhz murata erie csa2.00mg ?? 0.5% 4.0 mhz murata erie csa4.00mg ?? 0.5% 8.0 mhz murata erie csa8.00mt ? 0.5% 10.0 mhz murata erie csa10.00mtz ?? 0.5% none of the resonators had built-in capacitors. mode freq osc1/c1 osc2/c2 lp 32 khz 200 khz 68 - 100 pf 15 - 33 pf 68 - 100 pf 15 - 33 pf xt 100 khz 2 mhz 4 mhz 100 - 150 pf 15 - 33 pf 15 - 33 pf 100 - 150 pf 15 - 33 pf 15 - 33 pf hs 4 mhz 10 mhz 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : higher capacitance in creases the stability of oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci- fication. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. crystals tested: 32.768 khz epson c-001r32.768k-a ? 20 ppm 100 khz epson c-2 100.00 kc-p ? 20 ppm 200 khz std xtl 200.000 khz ? 20 ppm 1.0 mhz ecs ecs-10-13-2 ? 50 ppm 2.0 mhz ecs ecs-20-s-2 ? 50 ppm 4.0 mhz ecs ecs-40-s-4 ? 50 ppm 10.0 mhz ecs ecs-100-s-4 ? 50 ppm
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 37 8.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits are available; one with series resonance, and one with parallel resonance. figure 8-4 shows a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides negative feedback for stability. the 10 k ? potentiometer biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 8-4: external parallel resonant crystal oscillator circuit figure 8-5 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift. the 330 k ? resistors provide the negative feedback to bias the inverters in their linear region. figure 8-5: external series resonant crystal oscillator circuit 8.2.4 rc oscillator for timing insensitive applications the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) values, capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low cext values. the user needs to take into account variation due to tolerance of the external r and c components. figure 8-6 shows how an r/c combination is connected to the pic16c84. for rext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with little or no external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. see the electrical specification section for rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance has a greater affect on rc frequency). see the electrical specification section for variation of oscillator frequency due to v dd for given rext/cext values as well as frequency variation due to operating temperature. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test purposes or to synchronize other logic (see figure 3-2 for waveform). figure 8-6: rc oscillator mode 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16cxx clkin to other devices 330 k ? 74as04 74as04 pic16cxx clkin to other devices xtal 330 k ? 74as04 0.1 ?? f note: when the device oscillator is in rc mode, do not drive the osc1 pin with an external clock or you may damage the device. osc2/clkout cext rext pic16cxx osc1 fosc/4 internal clock v dd v ss recommended values: 3 k ? ? rext ? 100 k ? cext > 20pf
pic16c84 ds30445d-page 38 ? 1996-2013 microchip technology inc. 8.3 reset the pic16c84 differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) figure 8-7 shows a simplified block diagram of the on- chip reset circuit. the electrical specifications state the pulse width requirements for the mclr pin. some registers are not affected in any reset condition; their status is unknown on a por reset and unchanged in any other reset. most other registers are reset to a ?reset state? on por, mclr or wdt reset during normal operation and on mclr reset during sleep. they are not affected by a wdt reset during sleep, since this reset is viewed as the resumption of normal operation. table 8-3 gives a description of reset conditions for the program counter (pc) and the status register. table 8-4 gives a full description of reset states for all registers. the to and pd bits are set or cleared differently in dif- ferent reset situations (section 8.7). these bits are used in software to determine the nature of the reset. figure 8-7: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip rc osc (1) wdt time_out power_on_reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep clkin note 1: this is a separat e oscillator from the rc oscillator of the clkin pin. see table 8-5
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 39 table 8-3 reset condition for program counter and the status register condition program counter status register power-on reset 000h 0001 1xxx mclr reset during normal operation 000h 000u uuuu mclr reset during sleep 000h 0001 0uuu wdt reset (during normal operation) 000h 0000 1uuu wdt wake-up pc + 1 uuu0 0uuu interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu legend: u = unchanged, x = unknown. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). table 8-4 reset conditions for all registers register address power-on reset mclr reset during: ? normal operation ? sleep wdt reset during nor- mal operation wake-up from sleep: ? through interrupt ? through wdt time-out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h ---- ---- ---- ---- ---- ---- tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000h 0000h pc + 1 (2) status 03h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h ---x xxxx ---u uuuu ---u uuuu portb 06h xxxx xxxx uuuu uuuu uuuu uuuu eedata 08h xxxx xxxx uuuu uuuu uuuu uuuu eeadr 09h xxxx xxxx uuuu uuuu uuuu uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uuuu (1) indf 80h ---- ---- ---- ---- ---- ---- option_reg 81h 1111 1111 1111 1111 uuuu uuuu pcl 82h 0000h 0000h pc + 1 status 83h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 84h xxxx xxxx uuuu uuuu uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu eecon1 88h ---0 x000 ---0 q000 ---0 uuuu eecon2 89h ---- ---- ---- ---- ---- ---- pclath 8ah ---0 0000 ---0 0000 ---u uuuu intcon 8bh 0000 000x 0000 000u uuuu uuuu (1) legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. note 1: one or more bits in intcon will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: table 8-3 lists the reset value for each specific condition.
pic16c84 ds30445d-page 40 ? 1996-2013 microchip technology inc. 8.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v - 1.7v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create power-on reset. a minimum rise time for v dd must be met for this to operate properly. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, power-up trouble shooting . the por circuit does not produce an internal reset when v dd declines. 8.5 power-up timer (pwrt) the power-up timer (pwrt) provides a fixed 72 ms nominal time-out (t pwrt ) from por (figure 8-9, figure 8-10, figure 8-11 and figure 8-12). the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level (possible exception shown in figure 8-12). a configuration bit, pwrte, can enable/disable the pwrt (figure 8-1). the power-up time delay t pwrt will vary from chip to chip due to v dd , temperature, and process variation. see dc parameters for details. 8.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle delay (from osc1 input) after the pwrt delay ends (figure 8-9, figure 8-10, figure 8- 11 and figure 8-12). this ensures the crystal oscillator or resonator has started and stabilized. the ost time-out (t ost ) is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. when v dd rises very slowly, it is possible that the t pwrt time-out and t ost time-out will expire before v dd has reached its final value. in this case (figure 8- 12), an external power-on reset circuit may be neces- sary (figure 8-8). figure 8-8: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if v dd power-up rate is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that voltage drop across r does not exceed 0.2v (max leakage current spec on mclr pin is 5 ? a). a larger voltage drop will degrade v ih level on the mclr pin. 3: r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c in the event of an mclr pin breakdown due to esd or eos. c r1 r d v dd mclr pic16cxx v dd
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 41 figure 8-9: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 8-10: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
pic16c84 ds30445d-page 42 ? 1996-2013 microchip technology inc. figure 8-11: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 8-12: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por t pwrt t ost pwrt time-out ost time-out internal reset v dd mclr v1 when v dd rises very slowly, it is possible that the t pwrt time-out and t ost time-out will expire before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 ? v dd min. internal por t pwrt t ost pwrt time-out ost time-out internal reset
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 43 8.7 time-out sequence and power down status bits ( to / pd ) on power-up (figure 8-9, figure 8-10, figure 8-11 and figure 8-12) the time-out sequence is as follows: first pwrt time-out is invoked after a por has expired. then the ost is activated. the total time-out will vary based on oscillator configuration and pwrte configuration bit status. for example, in rc mode with the pwrt disabled, there will be no time-out at all. table 8-5 time-out in various situations since the time-outs occur from the por reset pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high, execution will begin immediately (figure 8-9). this is useful for testing purposes or to synchronize more than one pic16cxx device when operating in parallel. table 8-6 shows the significance of the to and pd bits. table 8-3 lists the reset conditions for some special registers, while table 8-4 lists the reset conditions for all the registers. table 8-6 status bits and their significance 8.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16c84 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 8-13 and figure 8-14. figure 8-13: brown-out protection circuit 1 figure 8-14: brown-out protection circuit 2 oscillator configuration power-up wake-up from sleep pwrt enabled pwrt disabled xt, hs, lp 72 ms + 1024t osc 1024t osc 1024t osc rc 72 ms ? ? to pd condition 11 power-on reset 0x illegal, to is set on por x0 illegal, pd is set on por 01 wdt reset (during normal operation) 00 wdt wake-up 11 mclr reset during normal operation 10 mclr reset during sleep or interrupt wake-up from sleep this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. v dd 33k 10k 40k v dd mclr pic16cxx this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd ? r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16cxx r1 q1 v dd
pic16c84 ds30445d-page 44 ? 1996-2013 microchip technology inc. 8.9 interrupts the pic16c84 has 4 sources of interrupt: ? external interrupt rb0/int pin ? tmr0 overflow interrupt ? portb change interrupts (pins rb7:rb4) ? eeprom write complete interrupt the interrupt control register (intcon) records individual interrupt requests in flag bits. it also contains the individual and global interrupt enable bits. the global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. bit gie is cleared on reset. the ?return from interrupt? instruction, retfie , exits interrupt routine as well as sets the gie bit, which re- enable interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. when an interrupt is responded to; the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. for external interrupt events, such as the rb0/int pin or portb change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency depends when the interrupt event occurs (figure 8-16). the latency is the same for both one and two cycle instructions. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid infinite interrupt requests. note 1: individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit. note 2: if an interrupt occurs while the global interrupt enable (gie) bit is being cleared, the gie bit may unintentionally be re- enabled by the user?s interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an instruction clears the gie bit while an interrupt is acknowledged 2. the program branches to the interrupt vector and executes the interrupt service routine. 3. the interrupt service routine completes with the execution of the retfie instruction. this causes the gie bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts. the method to ensure that interrupts are globally disabled is: 1. ensure that the gie bit is cleared by the instruction, as shown in the following code: loop bcf intcon,gie ;disable all ; interrupts btfsc intcon,gie ;all interrupts ; disabled? goto loop ;no, try again ; yes, continue ; with program ; flow
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 45 figure 8-15: interrupt logic figure 8-16: int pin interrupt timing rbif rbie t0if t0ie intf inte gie eeie wake-up (if in sleep mode) interrupt to cpu eeif q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 note 1: intf flag is sampled here (every q1). 2: interrupt latency = 3-4tcy where tcy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles. 2 3
pic16c84 ds30445d-page 46 ? 1996-2013 microchip technology inc. 8.9.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if intedg bit (option_reg<6>) is set, or falling, if intedg bit is clear. when a valid edge appears on the rb0/int pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing control bit inte (intcon<4>). flag bit intf must be cleared in software via the interrupt service routine before re-enabling this interrupt. the int interrupt can wake the processor from sleep (section 8.12) only if the inte bit was set prior to going into sleep. the status of the gie bit decides whether the processor branches to the interrupt vector following wake-up. 8.9.2 tmr0 interrupt an overflow (ffh ? 00h) in tmr0 will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (section 6.0). 8.9.3 port rb interrupt an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<3>) (section 5.2). 8.10 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users wish to save key register values during an interrupt (e.g., w register and status register). this is implemented in software. example 8-1 stores and restores the status and w register?s values. the user defined registers, w_temp and status_temp are the temporary storage locations for the w and status registers values. example 8-1 does the following: a) stores the w register. b) stores the status register in status_temp. c) executes the interrupt service routine code. d) restores the status (and bank select bit) register. e) restores the w register. example 8-1: saving status and w registers in ram push movwf w_temp ; copy w to temp register, swapf status, w ; swap status to be saved into w movwf status_temp ; save status to status_temp register isr : : : ; interrupt service routine : ; should configure bank as required : ; pop swapf status_temp, w ; swap nibbles in status_temp register ; and place result into w movwf status ; move w into status register ; (sets bank to original state) swapf w_temp, f ; swap nibbles in w_temp and place result in w_temp swapf w_temp, w ; swap nibbles in w_temp and place result into w note 1: if a change on an i/o pin should occur when a read operation of portb is being executed (start of the q2 cycle), the rbif interrupt flag bit may not get set.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 47 8.11 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation a wdt time-out generates a device reset. if the device is in sleep mode, a wdt wake-up causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming configuration bit wdte as a '0' (section 8.1). 8.11.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with temperature, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option_reg register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and pre- vent it from timing out and generating a device reset condition. the to bit in the status register will be cleared upon a wdt time-out. 8.11.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. figure 8-17: watchdog timer block diagram table 8-7 summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 2007h config. bits ? ? ? cp pwrte wdte fosc1 fosc0 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown. shaded cells are not used by the wdt. from tmr0 clock source (figure 6-6) to tmr0 (figure 6-6) postscaler wdt timer m u x psa 8 - to -1 mux psa wdt time-out 1 0 0 1 wdt enable bit ps2:ps0 ? ? 8 mux note: psa and ps2:ps0 are bits in the option_reg register.
pic16c84 ds30445d-page 48 ? 1996-2013 microchip technology inc. 8.12 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 8.12.1 sleep the power-down mode is entered by executing the sleep instruction. if enabled, the watchdog timer is cleared (but keeps running), the pd bit (status<3>) is cleared, the to bit (status<4>) is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for the lowest current consumption in sleep mode, place all i/o pins at either at v dd or v ss , with no external circuitry drawing current from the i/o pins, and disable external clocks. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss . the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). it should be noted that a reset generated by a wdt time-out does not drive the mclr pin low. 8.12.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. wdt wake-up (if wdt was enabled). 3. interrupt from rb0/int pin, rb port change, or data eeprom write complete. peripherals cannot generate interrupts during sleep, since no on-chip q clocks are present. the first event (mclr reset) will cause a device reset. the two latter events are considered a continuation of program execution. the to and pd bits can be used to determine the cause of a device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). while the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. figure 8-18: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will co ntinue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 49 8.12.3 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep . the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt post- scaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruc- tion was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. 8.13 program verification/code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 8.14 id locations four memory locations (2000h - 2003h) are designated as id locations to store checksum or other code identification numbers. these locations are not accessible during normal execution but are readable and writable only during program/verify. only the 4 least significant bits of id location are usable. for rom devices, these values are submitted along with the rom code. 8.15 in-circuit serial programming pic16c84 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. customers can manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product, allowing the most recent firmware or custom firmware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low, while raising the mclr pin from v il to v ihh (see pic16c84 eeprom memory programming specification (ds30189)). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/verify mode, the program counter (pc) points to location 00h. a 6-bit command is then supplied to the device, 14-bits of program data is then supplied to or from the device, using load or read-type instructions. for complete details of serial programming, please refer to the in-cir- cuit serial programming guide (ds30277). for rom devices, both the program memory and data eeprom memory may be read, but only the data eeprom memory may be programmed. figure 8-19: typical in-system serial programming connection note: microchip does not recommend code pro- tecting windowed devices.. external connector signals to n o r m a l connections to n o r m a l connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
pic16c84 ds30445d-page 50 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 51 9.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 9-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 9-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 9-1 opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 ? s. table 9-2 lists the instructions recognized by the mpasm assembler. figure 9-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 9-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of i talics user defined term (font is courier) note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c84 ds30445d-page 52 ? 1996-2013 microchip technology inc. table 9-2 pic16cxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tm r0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 53 9.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example: addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) + (f) ? (destination) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w= 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?ed with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal "k" process data write to w example andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) .and. (f) ? (destination) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w regis- ter. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
pic16c84 ds30445d-page 54 ? 1996-2013 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is executed. if bit 'b', in register 'f', is '0' then the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction . words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no-operat ion if skip: (2nd cycle) q1 q2 q3 q4 no-operat ion no-operati on no-opera tion no-operat ion example here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 55 btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is executed. if bit 'b' is '1', then the next instruction is discarded and a nop is executed instead, making this a 2t cy instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no-operat ion if skip: (2nd cycle) q1 q2 q3 q4 no-operat ion no-operati on no-opera tion no-operat ion example here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k', push pc to stack process data write to pc 2nd cycle no-opera tion no-opera tion no-opera tion no-operat ion example here call there before instruction pc = address here after instruction pc = address there tos = address here+1
pic16c84 ds30445d-page 56 ? 1996-2013 microchip technology inc. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0xxx xxxx description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no-opera tion process data write to w example clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no-opera tion process data clear wdt counter example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler= 0 to =1 pd =1
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 57 comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f ) ? (destination) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 1, the next instruction, is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruc- tion. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: (2nd cycle) q1 q2 q3 q4 no-operat ion no-opera tion no-operat ion no-operati on example here decfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt ? 0, pc = address here+1
pic16c84 ds30445d-page 58 ? 1996-2013 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k' process data write to pc 2nd cycle no-operat ion no-operat ion no-opera tion no-operat ion example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 59 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 1, the next instruction is executed. if the result is 0, a nop is exe- cuted instead making it a 2t cy instruc- tion . words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: (2nd cycle) q1 q2 q3 q4 no-operat ion no-opera tion no-opera tion no-operati on example here incfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt ? 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?ed with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=1
pic16c84 ds30445d-page 60 ? 1996-2013 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=1 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (destination) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependant upon the status of d. if d = 0, destination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file regis- ter since status flag z is affected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example movf fsr, 0 after instruction w = value in fsr register z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register . the don?t cares will assemble as 0?s. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example movwf option_reg before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 61 nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no-opera tion no-opera tion no-operat ion example nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code com- patibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode no-opera tion set the gie bit pop from the stack 2nd cycle no-operat ion no-opera tion no-opera tion no-operat ion example retfie after interrupt pc = tos gie = 1
pic16c84 ds30445d-page 62 ? 1996-2013 microchip technology inc. retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k' no-opera tion write to w, pop from the stack 2nd cycle no-operat ion no-opera tion no-opera tion no-operat ion example table call table ;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode no-opera tion no-opera tion pop from the stack 2nd cycle no-operat ion no-opera tion no-opera tion no-opera tion example return after interrupt pc = tos
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 63 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 1100 1100 c =1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example rrf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 register f c
pic16c84 ds30445d-page 64 ? 1996-2013 microchip technology inc. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 14.8 for more details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no-opera tion no-opera tion go to sleep example: sleep sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s comple- ment method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example 1: sublw 0x02 before instruction w= 1 c= ? z=? after instruction w= 1 c = 1; result is positive z=0 example 2: before instruction w= 2 c= ? z=? after instruction w= 0 c = 1; result is zero z=1 example 3: before instruction w= 3 c= ? z=? after instruction w= 0xff c = 0; result is negative z=0
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 65 subwf subtract w from f syntax: [ label ]subwf f,d operands: 0 ?? f ?? 127 d ? [0,1] operation: (f) - (w) ??? destination) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1: subwf reg1, 1 before instruction reg1 = 3 w=2 c=? z=? after instruction reg1 = 1 w=2 c = 1; result is positive z=0 example 2: before instruction reg1 = 2 w=2 c=? z=? after instruction reg1 = 0 w=2 c = 1; result is zero z=1 example 3: before instruction reg1 = 1 w=2 c=? z=? after instruction reg1 = 0xff w=2 c = 0; result is negative z=0 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x prod- ucts. since tris registers are read- able and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction.
pic16c84 ds30445d-page 66 ? 1996-2013 microchip technology inc. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .xor. (f) ??? destination) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example xorwf reg 1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
? 1996-2013 microchip technology inc. ds30445d - page 67 pic16c84 10.0 development support 10.1 development tools the picmicr ?? microcontrollers are supported with a full range of hardware and software development tools: ? picmaster ? /picmaster ce ? real-time in-circuit emulator ? icepic low-cost pic16c5x and pic16cxxx in-circuit emulator ?pro mate ? ii universal programmer ? picstart ? plus entry-level prototype programmer ? picdem-1 low-cost demonstration board ? picdem-2 low-cost demonstration board ? picdem-3 low-cost demonstration board ? mpasm assembler ? mplab ?? sim software simulator ? mplab-c (c compiler) ? fuzzy logic development system ( fuzzy tech ? ? mp) 10.2 picmaster: high performance universal in-circuit emulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the sx, pic14c000, pic16c5x, pic16cxxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?make? and download, and source debugging from a single envi- ronment. interchangeable target probes allow the system to be easily reconfigured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows ? 3.x environ- ment were chosen to best make these features avail- able to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 10.3 icepic: low-cost pic mcu in-circuit emulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at ? through pentium ? based machines under windows 3.x environment. ice- pic features real time, non-intrusive emulation. 10.4 pro mate ii: universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set configuration and code-protect bits in this mode. 10.5 p icstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket.
pic16c84 ds30445d - page 68 ? 1996-2013 microchip technology inc. 10.6 picdem-1 low-cost pic mcu demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchip?s microcon- trollers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the picmaster emulator and download the firmware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 10.7 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the picmaster emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 10.8 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the picmaster emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals. 10.9 mplab? integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: ? a full featured editor ? three operating modes -editor -emulator - simulator ? a project manager ? customizable tool bar and key mapping ? a status bar with project information ? extensive on-line help mplab allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic mcu tools (automatically updates all proj- ect information) ? debug using: - source files - absolute listing file ? transfer data dynamically via dde (soon to be replaced by ole) ? run up to four emulators on the same pc the ability to use mplab with microchip?s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 10.10 assembler (mpasm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from picmaster, microchip?s universal emulator system.
? 1996-2013 microchip technology inc. ds30445d - page 69 pic16c84 mpasm has the following features to assist in develop- ing software for specific use applications. ? provides translation of assembler source code to object code for all microchip microcontrollers. ? macro assembly capability. ? produces all the files (object, listing, symbol, and special) required for symbolic debug with microchip?s emulator systems. ? supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic mcu. directives are helpful in making the development of your assemble source code shorter and more maintainable. 10.11 s oftware simulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic mcu series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost flexibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 10.12 c compiler (mplab-c) the mplab-c code development system is a complete ?c? compiler and integrated development environment for microchip?s pic family of microcon- trollers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 10.13 fuzzy logic development system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchip?s fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 10.14 mp-driveway ? ? application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually configure all the peripherals in a pic device and, with a click of the mouse, generate all the initial- ization and many functional code modules in c lan- guage. the output is fully compatible with microchip?s mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 10.15 seeval ? evaluation and programming system the seeval seeprom designer?s kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 10.16 k ee l oq ? evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic16c84 ds30445d - page 70 ? 1996-2013 microchip technology inc. table 10-1: development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster ? / picmaster-ce in-circuit emulator ??? ? ????? available 3q97 icepic low-cost in-circuit emulator ?????? software tools mplab ? integrated development environment ??? ? ?????? mplab ? c compiler ??? ? ?????? fuzzy tech ? -mp explorer/edition fuzzy logic dev. tool ??? ? ????? mp-driveway ? applications code generator ????? ? total endurance ? software model ? programmers picstart ? lite ultra low-cost dev. kit ???? picstart ? plus low-cost universal dev. kit ??? ? ?????? pro mate ? ii universal programmer ??? ? ???????? keeloq ? programmer ? demo boards seeval ? designers kit ? picdem-1 ?? ? ? picdem-2 ?? picdem-3 ? keeloq ? evaluation kit ?
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 71 11.0 electrical characteristics for pic16c84 absolute maximum ratings ? ambient temperature under bias................................................................................................. ............-55 ? c to +125 ? c storage temperature ............................................................................................................ .................. -65 ? c to +150 ? c voltage on v dd with respect to v ss ............................................................................................................. -0.3 to +7.5v voltage on mclr with respect to v ss (2) .......................................................................................................-0.3 to +14v voltage on all other pins with respect to v ss .................................................................................. -0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw maximum current out of v ss pin ........................................................................................................................... 150 ma maximum current into v dd pin ........................................................................................................................... ...100 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????????? ?? 20 ma output clamp current, i ok (v o < 0 or v o >v dd ) ??????????????????????????????????????????????????????????????? ???????????????????????????????????????????????? ?? 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................20 ma maximum current sunk by ? porta .......................................................................................................................... 80 ma maximum current sourced by porta ............................................................................................... ......................50 ma maximum current sunk by portb.................................................................................................. ......................150 ma maximum current sourced by portb............................................................................................... ....................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c84 ds30445d-page 72 ? 1996-2013 microchip technology inc. table 11-1 cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16c84-04 pic16c84-10 pic16lc84-04 rc v dd : 4.0v to 6.0v i dd : 4.5 ma max. at 5.5v i pd : 100 ? a max. at 4.0v wdt dis freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 40.0 ? a typ. at 4.5v wdt dis freq: 4.0 mhz max. v dd : 2.0v to 6.0v i dd : 4.5 ma max. at 5.5v i pd : 100 ? a max. at 4v wdt dis freq: 2.0 mhz max. xt v dd : 4.0v to 6.0v i dd : 4.5 ma max. at 5.5v i pd : 100 ? a max. at 4.0v wdt dis freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 40.0 ? a typ. at 4.5v wdt dis freq: 4.0 mhz max. v dd : 2.0v to 6.0v i dd : 4.5 ma max. at 5.5v i pd : 100 ? a max. at 4v wdt dis freq: 2.0 mhz max. hs v dd : 4.5v to 5.5v i dd : 4.5 ma typ. at 5.5v i pd : 40.0 ? a typ. at 4.5v wdt dis freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 10 ma max. at 5.5v typ. freq: 10 mhz max. do not use in hs mode lp v dd : 4.0v to 6.0v i dd : 60 ? a typ. at 32 khz, 2.0v i pd : 26 ? a typ. at 2.0v wdt dis freq: 200 khz max. do not use in lp mode v dd : 2.0v to 6.0v i dd : 400 ? a max. at 32 khz, 2.0v i pd : 100 ? a max. at 4.0v wdt dis freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max specifications. it i s recommended that the user select the device type that ensures the s pecifications required. i pd : 40.0 ? a typ. at 4.5v wdt dis
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 73 11.1 dc characteristics: pic16c84-04 (commercial, industrial) pic16c84-10 (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 ? c ? t a ? +70 ? c (commercial) -40 ? c ? t a ? +85 ? c (industrial) parame- ter no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 4.5 ? ? 6.0 5.5 v v xt, rc and lp osc configuration hs osc configuration d002 v dr ram data retention voltage (1) 1.5* ? ? v device in sleep mode d003 v por v dd start voltage to ensure internal power- on reset signal ?v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05* ? ? v/ms see section on power-on reset for details d010 d010a d013 i dd supply current (2) ? ? ? 1.8 7.3 5.0 4.5 10 10 ma ma ma rc and xt osc configuration (4) f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v (during eeprom programming) hs osc configuration (pic16c84-10) f osc = 10 mhz, v dd = 5.5v d020 d021 d021a i pd power-down current (3) ? ? ? 40 38 38 100 100 100 ? a ? a ? a v dd = 4.0v, wdt enabled, industrial v dd = 4.0v, wdt disabled, commercial v dd = 4.0v, wdt disabled, industrial * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through rext is not included. the current through the resistor can be estimated by the formula i r = v dd /2rext (ma) with rext in kohm.
pic16c84 ds30445d-page 74 ? 1996-2013 microchip technology inc. 11.2 dc characteristics pic16lc84-04 (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 ? c ? t a ? +70 ? c (commercial) -40 ? c ? t a ? +85 ? c (industrial) parameter no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.0 ? 6.0 v xt, rc, and lp osc configuration d002 v dr ram data retention voltage (1) 1.5 * ? ? v device in sleep mode d003 v por v dd start voltage to ensure internal power- on reset signal ?v ss ? v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05* ? ? v/ms see section on power-on reset for details d010 d010a d014 i dd supply current (2) ? ? ? 1 7.3 60 4 10 400 ma ma ? a rc and xt osc configuration (4) f osc = 2 mhz, v dd = 5.5v f osc = 2 mhz, v dd = 5.5v (during eeprom programming) lp osc configuration f osc = 32 khz, v dd = 2.0v, wdt disabled d020 d021 d021a i pd power-down current (3) ? ? ? 26 26 26 100 100 100 ? a ? a ? a v dd = 2.0v, wdt enabled, industrial v dd = 2.0v, wdt disabled, commercial v dd = 2.0v, wdt disabled, industrial * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through rext is not included. the current through the resistor can be estimated by the formula i r = v dd /2rext (ma) with rext in kohm.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 75 11.3 dc characteristics: pic16c84-04 (commercial, industrial) pic16c84-10 (commercial, industrial) pic16lc84-04 (commercial, industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 ? c ? t a ? +70 ? c (commercial) -40 ? c ? t a ? +85 ? c (industrial) operating voltage v dd range as described in dc spec section 11- 1 and section 11.2. parameter no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss ?0.8 v4.5 ?? v dd ?? 5.5v d030a v ss ? 0.16v dd v entire range (4) d031 with schmitt trigger buffer v ss ?0.2v dd v entire range d032 mclr , ra4/t0cki, osc1 (rc mode) vss ? 0.2v dd v d033 osc1 (xt, hs and lp modes) (1) vss ? 0.3v dd v input high voltage v ih i/o ports d040 with ttl buffer 0.36v dd ?v dd v4.5 ?? v dd ?? 5.5v d040a 0.48v dd entire range (4) d041 with schmitt trigger buffer 0.45v dd ?v dd entire range d042 mclr , ra4/t0cki, osc1 (rc mode) 0.85v dd ?v dd v d043 osc1 (xt, hs and lp modes) (1) 0.7v dd ?v dd v d070 i purb portb weak pull-up current 50* 250* 400* ? av dd = 5v, v pin = v ss input leakage current (2,3) d060 i il i/o ports ? ? ? 1 ? avss ?? v pin ?? v dd , pin at hi-impedance d061 mclr , ra4/t0cki ? ? ? 5 ? avss ?? v pin ?? v dd d063 osc1/clkin ? ? ? 5 ? avss ?? v pin ?? v dd , xt, hs and lp osc configuration output low voltage d080 v ol i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v d083 osc2/clkout ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v (rc osc configuration) output high voltage d090 v oh i/o ports (3) v dd - 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v d093 osc2/clkout v dd - 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v (rc osc configuration) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c84 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: the user may use better of the two specs.
pic16c84 ds30445d-page 76 ? 1996-2013 microchip technology inc. 11.4 dc characteristics: pic16c84-04 (commercial, industrial) pic16c84-10 (commercial, industrial) pic16lc84-04 (commercial, industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise stated) operating temperature 0 ? c ? t a ? +70 ? c (commercial) -40 ? c ? t a ? +85 ? c (industrial) operating voltage v dd range as described in dc spec section 11-1 and section 11.2. parameter no. sym characteristic min typ? max units conditions capacitive loading specs on output pins d100 c osc2 osc2/clkout pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (rc mode) ? ? 50 pf data eeprom memory d120 e d endurance 1m 10m ? e/w 25 ? c at 5v d121 v drw v dd for read/write v min ?6.0vv min = minimum operating voltage d122 t dew erase/write cycle time (1) ?1020*ms program eeprom memory d130 e p endurance 100 1000 ? e/w d131 v pr v dd for read v min ?6.0vv min = minimum operating voltage d132 v pew v dd for erase/write 4.5 ? 5.5 v d133 t pew erase/write cycle time (1) ?10?ms * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the user should use interrupts or poll the eeif or wr bits to ensure the write cycle has completed.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 77 table 11-2 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 11-1: parameter measurement information figure 11-2: load conditions 1. tpps2pps 2. tpps t ffrequency ttime lowercase symbols (pp) and their meanings: pp 2to os,oscosc1 ck clkout ost oscillator start-up timer cy cycle time pwrt power-up timer io i/o port rbt rbx pins inp int pin t0 t0cki mc mclr wdt watchdog timer uppercase symbols and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance all timings are measured between high and low measurement points as indicated in the figure. 2.0 v dd (high) 0.2 v dd (low) 0.8 v dd rc 0.3 v dd xtal osc1 measurement points i/o port measurement points 0.15 v dd rc 0.7 v dd xtal (high) (low) load condition 1 load condition 2 pin r l c l v ss v dd /2 v ss c l pin r l = 464 ? c l = 50 pf for all pins except osc2. 15 pf for osc2 output.
pic16c84 ds30445d-page 78 ? 1996-2013 microchip technology inc. 11.5 timing diagrams and specifications figure 11-3: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 13344 2 table 11-3 external clock timing requirements parameter no. sym characteristic min typ? max units conditions f osc external clkin frequency (1) dc ? 2 mhz xt, rc osc pic16lc84-04 dc ? 4 mhz xt, rc osc pic16c84-04 dc ? 10 mhz hs osc pic16c84-10 dc ? 200 khz lp osc pic16lc84-04 oscillator frequency (1) dc ? 2 mhz rc osc pic16lc84-04 dc ? 4 mhz rc osc pic16c84-04 0.1 ? 2 mhz xt osc pic16lc84-04 0.1 ? 4 mhz xt osc pic16c84-04 1 ? 10 mhz hs osc pic16c84-10 dc ? 200 khz lp osc pic16lc84-04 1tosc external clkin period (1) 500 ? ? ns xt, rc osc pic16lc84-04 250 ? ? ns xt, rc osc pic16c84-04 100 ? ? ns hs osc pic16c84-10 5? ? ? s lp osc pic16lc84-04 oscillator period (1) 500 250 ? ? ? ? ns ns rc osc pic16lc84-04 rc osc pic16c84-04 500 ? 10,000 ns xt osc pic16lc84-04 250 ? 10,000 ns xt osc pic16c84-04 100 ? 1,000 ns hs osc pic16c84-10 5? ? ? s lp osc pic16lc84-04 2t cy instruction cycle time (1) 0.4 4/fosc dc ? s 3 tosl, to s h clock in (osc1) high or low time 60 * ? ? ns xt osc pic16lc84-04 50 * ? ? ns xt osc pic16c84-04 2 * ? ? ? s lp osc pic16lc84-04 35 * ? ? ns hs osc pic16c84-10 4tosr, to s f clock in (osc1) rise or fall time 25 * ? ? ns xt osc pic16c84-04 50 * ? ? ns lp osc pic16lc84-04 15 * ? ? ns hs osc pic16c84-10 * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25c unless otherwise st ated. these parameters are fo r design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particula r oscillator type under standard operating conditi ons with the device executing code. exceeding these specified limits may result in an unstab le oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1 pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 79 figure 11-4: clkout a nd i/o timing table 11-4 clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 ? to clkout ? pic16c84 ? 15 30 * ns note 1 10a pic16lc84 ? 15 120 * ns note 1 11 tosh2ckh osc1 ? to clkout ? pic16c84 ? 15 30 * ns note 1 11a pic16lc84 ? 15 120 * ns note 1 12 tckr clkout rise time pic16c84 ? 15 30 * ns note 1 12a pic16lc84 ? 15 100 * ns note 1 13 tckf clkout fall time pic16c84 ? 15 30 * ns note 1 13a pic16lc84 ? 15 100 * ns note 1 14 tckl2iov clkout ? to port out valid ? ? 0.5t cy +20 * ns note 1 15 tiov2ckh port in valid before pic16c84 0.30t cy + 30 * ? ? ns note 1 clkout ? pic16lc84 0.30t cy + 80 * ? ? ns note 1 16 tckh2ioi port in hold after clkout ? 0 * ? ? ns note 1 17 tosh2iov osc1 ? (q1 cycle) to pic16c84 ? ? 125 * ns port out valid pic16lc84 ? ? 250 * ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time pic16c84 ? 10 25 * ns 20a pic16lc84 ? 10 60 * ns 21 tiof port output fall time pic16c84 ? 10 25 * ns 21a pic16lc84 ? 10 60 * ns 22 tinp int pin high pic16c84 20 * ? ? ns 22a or low time pic16lc84 55 * ? ? ns 23 trbp rb7:rb4 change int pic16c84 20 * ? ? ns 23a high or low time pic16lc84 55 * ? ? ns * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value note: all tests must be done with specified capacitive loads (figure 11-2) 50 pf on i/o pins and clkout.
pic16c84 ds30445d-page 80 ? 1996-2013 microchip technology inc. figure 11-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 11-5 reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 350 * 150 * ? ? ? ? ns ns 2.0v ? v dd ? 3.0v 3.0v ? v dd ? 6.0v 31 twdt watchdog timer time-out period (no prescaler) 7 * 18 33 * ms v dd = 5v 32 tost oscillation start-up timer period ? 1024t osc ?mst osc = osc1 period 33 tpwrt power-up timer period 28 * 72 132 * ms v dd = 5.0v 34 t ioz i/o hi-impedance from mclr low or reset ? ? 100 * ns * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 ? c unless otherwise stated. these parameter s are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 81 figure 11-6: timer0 clock timings table 11-6 timer0 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 * ? ? ns with prescaler 50 * 30 * ? ? ? ? ns ns 2.0v ? v dd ? 3.0v 3.0v ? v dd ? 6.0v 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 * ? ? ns with prescaler 50 * 20 * ? ? ? ? ns ns 2.0v ? v dd ? 3.0v 3.0v ? v dd ? 6.0v 42 tt0p t0cki period t cy + 40 * n ? ? ns n = prescale value (2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. ra4/t0cki 40 41 42
pic16c84 ds30445d-page 82 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 83 12.0 dc & ac characteristics graphs/tables for pic16c84 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25 ? c, while 'max' or 'min' represents (mean + 3 ? ) and (mean - 3 ? ) respectively, where ? is standard deviation. figure 12-1: typical rc oscillator frequency vs. temperature table 12-1 rc oscillator frequencies * *measured in pdip packages.the percentage variation indicated here is part to part variation due to normal process distribution. the variation indicated is ? 3 standard deviation from average value. cext rext average fosc @ 5v, 25 ? c 20 pf 3.3k 4.68 mhz ? 27% 5.1k 3.94 mhz ? 25% 10k 2.34 mhz ? 29% 100k 250.16 khz ? 33% 100 pf 3.3k 1.49 mhz ? 25% 5.1k 1.12 mhz ? 25% 10k 620.31 khz ? 30% 100k 90.25 khz ? 26% 300 pf 3.3k 524.24 khz ? 28% 5.1k 415.52 khz ? 30% 10k 270.33 khz ? 26% 100k 25.37 khz ? 25% f osc f osc (25 ? c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( ? c) frequency normalized to +25 ? c v dd = 5.5v v dd = 3.5v rext ? 10 k ? cext = 100 pf 0.88
pic16c84 ds30445d-page 84 ? 1996-2013 microchip technology inc. figure 12-2: typical rc oscillator frequency vs. v dd (cext = 20 pf) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5.5 f osc (mhz) v dd (volts) 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 rext = 3.3k rext = 5k t = 25 ? c 2.0 2.5 rext = 100k rext = 10k
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 85 figure 12-3: typical rc oscillator frequency vs. v dd (cext = 100 pf) figure 12-4: typical rc oscillator frequency vs. v dd (cext = 300 pf) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.2 f osc (mhz) v dd (volts) 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 rext = 3.3k rext = 5k rext = 10k 2.0 2.5 t = 25 ? c rext = 100k 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.1 f osc (mhz) v dd (volts) 0.1 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 rext = 3.3k rext = 5k rext = 10k rext = 100k 2.0 2.5 t = 25 ? c
pic16c84 ds30445d-page 86 ? 1996-2013 microchip technology inc. figure 12-5: typical i pd vs. v dd watchdog disabled (25c) figure 12-6: typical i pd vs. v dd watchdog enabled (25c) 60 50 40 30 20 3.5 4.0 4.5 5.0 5.5 i pd ( ? a) v dd (volts) 10 0 6.0 3.0 2.5 2.0 60 50 40 30 20 3.5 4.0 4.5 5.0 5.5 i pd ( ? a) v dd (volts) 10 0 6.0 3.0 2.5 2.0
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 87 figure 12-7: maximum i pd vs. v dd watchdog disabled figure 12-8: maximum i pd vs. v dd watchdog enabled* * i pd , with watchdog timer enabled, has two components: the leakage current which increases with higher temperature and the operating current of the watchdog timer logic which increases with lower temperature. at -40 ? c, the latter dominates explaining the apparently anomalous behavior. 120 100 80 60 40 3.5 4.0 4.5 5.0 5.5 i pd ( ? a) v dd (volts) 20 0 6.0 3.0 2.5 2.0 m a x . t e m p . = 8 5 ? c t y p . t e m p . = 2 5 ? c m i n . t e m p . = - 4 0 ? c 120 100 80 60 40 3.5 4.0 4.5 5.0 5.5 i pd ( ? a) v dd (volts) 20 0 6.0 3.0 2.5 2.0 m a x . t e m p . = 8 5 ? c t y p . t e m p . = 2 5 ? c m i n . t e m p . = - 4 0 ? c
pic16c84 ds30445d-page 88 ? 1996-2013 microchip technology inc. figure 12-9: v th (input threshold voltage) of i/o pins vs. v dd figure 12-10: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.5 v th (volts) v dd (volts) 0.6 max (-40 ? c to +85 ? c) ty p @ 2 5 ? c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 min (-40 ? c to +85 ? c) v th (volts) v dd (volts) 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.2 1.4 1.6 1.8 2.0 2.2 2.4 6.0 2.6 2.8 3.0 m i n ( - 4 0 ? c t o + 8 5 ? c ) 3.2 3.4 m a x ( - 4 0 ? c t o + 8 5 ? c ) t y p ( 2 5 ? c )
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 89 figure 12-11: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd 2.0 v ih , v il (volts) v dd (volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 4.0 4.5 5.0 v ih , max (-40 ? c to +85 ? c) v ih , typ (25 ? c) v ih , min (-40 ? c to +85 ? c) v il , max (-40 ? c to +85 ? c) v il , typ (25 ? c) v il , min (-40 ? c to +85 ? c)
pic16c84 ds30445d-page 90 ? 1996-2013 microchip technology inc. figure 12-12: typical i dd vs. freq (ext clock, 25c) figure 12-13: maximum i dd vs. freq (ext clock, -40 to +85c) 10k 100k 1m 10m 100m 10 100 1,000 10,000 i dd ( ? a) external clock frequency (hz) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 10k 100k 1m 10m 100m 10 100 1,000 10,000 i dd ( ? a) external clock frequency (hz) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 91 figure 12-14: wdt time-out period vs. v dd figure 12-15: transconductance (g m) of hs oscillator vs. v dd 70 60 50 40 30 2.5 3.5 4.0 4.5 5.0 v dd (volts) 20 10 5.5 6.0 wdt time-out period (ms) max. 70 ? c min. -40 ? c 3.0 2.0 0 min. 0 ? c ty p. 2 5 ? c max. 85 ? c 10000 9000 8000 7000 6000 5000 4000 3000 2000 2.0 3.5 3.0 3.5 4.0 4.5 gm( ? a/v) v dd (volts) min @ 85 ? c 1000 0 5.0 5.5 max @ -40 ? c typ @ 25 ? c
pic16c84 ds30445d-page 92 ? 1996-2013 microchip technology inc. figure 12-16: transconductance (g m) of lp oscillator vs. v dd figure 12-17: transconductance (g m) of xt oscillator vs. v dd 250 225 200 175 150 125 100 75 50 2.0 2.5 3.0 3.5 4.0 4.5 gm( ? a/v) v dd (volts) min @ 85 ? c 25 0 5.0 5.5 max @ -40 ? c ty p @ 2 5 ? c 2000 1800 1600 1400 1200 1000 800 600 400 2.0 2.5 3.0 3.5 4.0 4.5 gm( ? a/v) v dd (volts) min @ 85 ? c 200 0 5.0 5.5 max @ -40 ? c ty p @ 2 5 ? c
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 93 figure 12-18: i oh vs. v oh , v dd = 3v figure 12-19: i oh vs. v oh , v dd = 5v 0 -2 -4 -6 -8 -10 -12 -14 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v oh (volts) min @ 85 ? c -16 -18 3.0 max @ -40 ? c typ @ 25 ? c 0 -5 -10 -15 -20 -25 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v oh (volts) min @ 85 ? c -30 -35 3.0 max @ -40 ? c typ @ 25 ? c 3.5 4.0 4.5 5.0 -40 -45
pic16c84 ds30445d-page 94 ? 1996-2013 microchip technology inc. figure 12-20: i ol vs. v ol , v dd = 3v figure 12-21: i ol vs. v ol , v dd = 5v 30 25 20 15 10 0.0 0.5 1.0 1.5 2.0 v ol (volts) 5 0 2.5 3.0 i ol (ma) min. +85 ? c ty p. 2 5 ? c max. -40 ? c 35 90 80 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 i ol (ma) v ol (volts) min @ +85 ? c 10 0 3.0 max @ -40 ? c ty p @ 2 5 ? c
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 95 figure 12-22: maximum data memory erase/write cycle time vs. vdd table 12-2 input capacitance* 14 12 10 8 6 4 2 0 2.53.03.54.04.55.05.5 6.0 dmem max. e/w cycle time (ms) v dd (volts) 6.5 1.5 2.0 20 18 16 shaded areas are beyond recommended range. pin name typical capacitance (pf) 18l pdip 18l soic porta 5.0 4.3 portb 5.0 4.3 mclr 17.0 17.0 osc1/clkin 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 * all capacitance values are typical at 25 ? c. a part to part variation of ? 25% (three standard deviations) should be taken into account.
pic16c84 ds30445d-page 96 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 97 13.0 packaging information 13.1 k04-007 18-lead plastic dual in-line (p) ? 300 mil * controlling parameter. ? dimension ?b1? does not include dam-bar protru sions. dam-bar protrusions shall not exceed 0.003? (0.076 mm) per side or 0.006? (0.152 mm) more than dimension ?b1.? ? dimensions ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010? (0.254 mm) per side or 0.020? (0.508 mm) more than dimensions ?d? or ?e.? units inches* millimeters dimension limits min nom max min nom max pcb row spacing 0.300 7.62 number of pins n 18 18 pitch p 0.100 2.54 lower lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thickness c 0.005 0.010 0.015 0.13 0.25 0.38 top to seating plane a 0.110 0.155 0.155 2.79 3.94 3.94 top of lead to seating plane a1 0.075 0.095 0.115 1.91 2.41 2.92 base to seating plane a2 0.000 0.020 0.020 0.00 0.51 0.51 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 package length d ? 0.890 0.895 0.900 22.61 22.73 22.86 molded package width e ? 0.245 0.255 0.265 6.22 6.48 6.73 radius to radius width e1 0.230 0.250 0.270 5.84 6.35 6.86 overall row spacing eb 0.310 0.349 0.387 7.87 8.85 9.83 mold draft angle top ? 51015 51015 mold draft angle bottom ? 51015 51015 r n 2 1 d e c eb ? e1 ? p a1 l b1 b a a2 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c84 ds30445d-page 98 ? 1996-2013 microchip technology inc. 13.2 k04-051 18-lead plastic small outline (so) ? wide, 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 min n number of pins mold draft angle bottom mold draft angle top lower lead width chamfer distance outside dimension molded package width molded package length overall pack. height lead thickness radius centerline foot angle foot length gull wing radius shoulder radius standoff shoulder height ? ? r2 r1 e1 a2 a1 x ? b ? c l1 l e ? d ? a dimension limits pitch units p 18 18 0 0 12 12 15 15 4 0.020 0 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 8 0.419 0.299 0.462 0.011 0.068 0.104 0 0 12 12 15 15 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 48 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 inches* 0.050 nom max 1.27 millimeters min nom max n 2 1 r2 r1 l1 l ? c ? x 45 d p b e e1 ? a1 a2 a * controlling parameter. ? dimension ?b? does not include dam-bar protrusions . dam-bar protrusions s hall not exceed 0.003? (0.076 mm) per side or 0.006? (0.152 mm) more than dimension ?b.? ? dimensions ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010? (0.254 mm) per side or 0.020? (0.508 mm) more than dimensions ?d? or ?e.? note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 99 appendix a: feature improvements - from pic16c5x to pic16c84 the following is the list of feature improvements over the pic16c5x microcontroller family: 1. instruction word length is increased to 14 bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). 2. a pc latch register (pclath) is added to handle program memory paging. pa2, pa1 and pa0 bits are removed from the status register and placed in the option register. 3. data memory paging is redefined slightly. the status register is modified. 4. four new instructions have been added: return , retfie , addlw , and sublw . two instructions, tris and option, are being phased out although they are kept for compatibility with pic16c5x. 5. option and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. registers are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, the oscillator start-up timer (ost) and power-up timer (pwrt), are included for more reliable power-up. these timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change features. 13. t0cki pin is also a port pin (ra4/t0cki). 14. fsr is a full 8-bit register. 15. "in system programming" is made possible. the user can program pic16cxx devices using only five pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). appendix b: code compatibility - from pic16c5x to pic16c84 to convert code written for pic16c5x to pic16c84, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables for reallocation. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16c84 ds30445d-page 100 ? 1996-2013 microchip technology inc. appendix c: what?s new in this data sheet no new information has been added to this data sheet. for information on upgrade devices from the pic16c84, please refer to the pic16f8x data sheet. appendix d: what?s changed in this data sheet here?s what?s changed in this data sheet: 1. some sections have been rearranged for clarity and consistency. 2. errata information has been included. revision d (january 2013) added a note to each package drawing.
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 101 appendix e: conversion co nsiderations - pic16c84 to pic16f83/f84 and pic16cr83/cr84 considerations for converting from the pic16c84 to the pic16f84 are listed in the table below. these con- siderations apply to converting from the pic16c84 to the pic16f83 (same as pic16f84 except for program and data ram memory sizes) and the pic16cr84 and pic16cr83 (rom versions of flash devices). devel- opment systems support is available for all of the pic16x8x devices. difference pic16c84 pic16f84 the polarity of the pwrte bit has been reversed. ensure that the pro- grammer has this bit correctly set before programming. pwrte pwrte the pic16f84 (and pic16cr84) have larger ram sizes. ensure that this does not cause an issue with your program. ram = 36 bytes ram = 68 bytes the mclr pin now has an on-chip filter. the input signal on the mclr pin will require a longer low pulse to generate an interrupt. mclr pulse width (low) = 350ns; 2.0v ? v dd ? 3.0v = 150ns; 3.0v ? v dd ? 6.0v mclr pulse width (low) = 1000ns; 2.0v ? v dd ? 6.0v some electrical specifications have been improved (see i pd example). compare the electrical specifica- tions of the two devices to ensure that this will not cause a compatibil- ity issue. i pd (typ @ 2v) = 26 ? a i pd (max @ 4v, wdt disabled) =100 ? a (pic16c84) =100 ? a (pic16lc84) i pd (typ @ 2v) < 1 ? a i pd (max @ 4v, wdt disabled) =14 ? a (pic16f84) =7 ? a (pic16lf84) porta and crystal oscillator values less than 500khz for crystal oscillator configurations operating below 500khz, the device may generate a spurious internal q- clock when porta<0> switches state. n/a rb0/int pin ttl ttl/st* (* this buffer is a schmitt trigger input when configured as the exter- nal interrupt.) eeadr<7:6> and i dd it is recommended that the eeadr<7:6> bits be cleared. when either of these bits is set, the maximum i dd for the device is higher than when both are cleared. n/a code protect 1 cp bit 9 cp bits recommended value of r ext for rc oscillator circuits r ext = 3k ? - 100k ? r ext = 5k ? - 100k ? gie bit unintentional enable if an interrupt occurs while the global interrupt enable (gie) bit is being cleared, the gie bit may unin- tentionally be re-enabled by the user?s interrupt service routine (the retfie instruction). n/a
pic16c84 ds30445d-page 102 ? 1996-2013 microchip technology inc. notes:
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 103 index a absolute maximum ratings ............................................... 71 alu ...................................................................................... 7 architectural overview ......................................................... 7 assembler mpasm assembler .................................................... 68 b block diagram interrupt logic ............................................................ 45 on-chip reset circuit ................................................ 38 ra3:ra0 and ra5 port pins ..................................... 19 ra4 pin ...................................................................... 19 rb3:rb0 port pins .................................................... 21 rb7:rb4 port pins .................................................... 21 tmr0/wdt prescaler ................................................ 28 watchdog timer ......................................................... 47 brown-out protection circuit .............................................. 43 c carry .................................................................................... 7 clkin .................................................................................. 9 clkout .............................................................................. 9 code protection ........................................................... 35, 49 compatibility, upward ........................................................... 3 computed goto ............................................................... 17 configuration bits ............................................................... 35 d dc characteristics ........................................... 73, 74, 75, 76 development support ........................................................ 67 development tools ............................................................ 67 digit carry ............................................................................ 7 e external power-on reset circuit ........................................ 40 f family of devices pic16c8x .................................................................... 4 fsr .............................................................................. 18, 39 fuzzy logic dev. system ( fuzzy tech ? -mp) ................... 69 g gie ..................................................................................... 44 i i/o ports ............................................................................. 19 i/o programming considerations ....................................... 23 icepic low-cost pic16cxxx in-circuit emulator ........... 67 in-circuit serial programming ...................................... 35, 49 indf ................................................................................... 39 instruction format .............................................................. 51 instruction set addlw ...................................................................... 53 addwf ...................................................................... 53 andlw ...................................................................... 53 andwf ...................................................................... 53 bcf ............................................................................ 54 bsf ............................................................................ 54 btfsc ....................................................................... 54 btfss ....................................................................... 55 call .......................................................................... 55 clrf .......................................................................... 56 clrw ........................................................................ 56 clrwdt ................................................................... 56 comf ........................................................................ 57 decf ......................................................................... 57 decfsz .................................................................... 57 goto ........................................................................ 58 incf .......................................................................... 58 incfsz ...................................................................... 59 iorlw ....................................................................... 59 iorwf ....................................................................... 60 movf ........................................................................ 60 movlw ..................................................................... 60 movwf ..................................................................... 60 nop ........................................................................... 61 option ..................................................................... 61 retfie ...................................................................... 61 retlw ...................................................................... 62 return .................................................................... 62 rlf ............................................................................ 63 rrf ........................................................................... 63 sleep ....................................................................... 64 sublw ...................................................................... 64 subwf ...................................................................... 65 swapf ...................................................................... 65 tris .......................................................................... 65 xorlw ..................................................................... 66 xorwf ..................................................................... 66 section ....................................................................... 51 summary table ......................................................... 52 int interrupt ...................................................................... 46 intcon ........................................................... 16, 39, 44, 46 intedg ............................................................................. 46 interrupts flag ............................................................................ 44 interrupt on change feature ..................................... 21 interrupts ............................................................. 35, 44 k keeloq ? evaluation and programming tools .................. 69 l loading of pc .................................................................... 17 m mclr ...................................................................... 9, 38, 39 memory organization data memory ............................................................. 12 memory organization ................................................ 11 program memory ....................................................... 11 mp-driveway? - application code generator ................. 69 mplab c ........................................................................... 69 mplab integrated development environment software ... 68 o opcode ........................................................................... 51 option_reg ....................................................... 15, 39, 46 osc selection .................................................................... 35 osc1 ................................................................................... 9 osc2 ................................................................................... 9 oscillator hs ........................................................................ 36, 43 lp ........................................................................ 36, 43 rc ....................................................................... 36, 37 xt ........................................................................ 36, 43 oscillator configurations ............... ..................................... 36 p paging, program memory .................................................. 17
pic16c84 ds30445d-page 104 ? 1996-2013 microchip technology inc. pcl .............................................................................. 17, 39 pclath ....................................................................... 17, 39 pd .......................................................................... 14, 38, 43 picdem-1 low-cost pic mcu demo board .................... 68 picdem-2 low-cost pic16cxx demo board .................. 68 picdem-3 low-cost pic16cxxx demo board ................ 68 picmaster ? in-circuit emulator ..................................... 67 picstart ? plus entry level development system ........ 67 pinout descriptions .............................................................. 9 por ................................................................................... 40 oscillator start-up timer (ost) ........................... 35, 40 power-on reset (por) .................................. 35, 39, 40 power-up timer (pwrt) ..................................... 35, 40 time-out sequence .................................................... 43 time-out sequence on power-up .............................. 41 to .................................................................. 14, 38, 43 port rb interrupt ................................................................ 46 porta ..................................................................... 9, 19, 39 portb ..................................................................... 9, 21, 39 power-down mode (sleep) .............................................. 48 prescaler ............................................................................ 27 pro mate ? ii universal programmer .............................. 67 product identification system ........................................... 107 r rbif bit ........................................................................ 21, 46 rc oscillator ...................................................................... 43 read-modify-write ............................................................. 23 register file ....................................................................... 12 reset ............................................................................ 35, 38 reset on brown-out ........................................................... 43 s saving w register and status in ram .......................... 46 seeval ? evaluation and programming system .............. 69 sleep .................................................................... 35, 38, 48 software simulator (mplab-sim) ...................................... 69 special features of the cpu .............................................. 35 special function registers ................................................ 12 stack .................................................................................. 17 overflows ................................................................... 17 underflows ................................................................. 17 status ................................................................... 7, 14, 39 t time-out .............................................................................. 39 timer0 switching prescaler assignment ................................ 29 t0if ............................................................................ 46 timer0 module ........................................................... 25 tmr0 interrupt ........................................................... 46 tmr0 with external clock .......................................... 27 timing diagrams time-out sequence .................................................... 41 timing diagrams and specifications .................................. 78 trisa ................................................................................. 19 trisb ........................................................................... 21, 39 w w ........................................................................................ 39 wake-up from sleep .................................................. 39, 48 watchdog timer (wdt) ................................... 35, 38, 39, 47 wdt ................................................................................... 39 period ......................................................................... 47 programming considerations .................................... 47 time-out ..................................................................... 39 z zero bit ................................................................................. 7
? 1996-2013 microchip tec hnology inc. ds30445d-page 11-105 pic16c84 on-line support microchip provides two methods of on-line support. these are the microchip bbs and the microchip world wide web (www) site. use microchip's bulletin board service (bbs) to get current information and help about microchip products. microchip provides the bbs communication channel for you to use in extending your technical staff with microcontroller and memory experts. to provide you with the most responsive service possible, the microchip systems team monitors the bbs, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how microchip products pro- vide project solutions. the web site, like the bbs, is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp.mchip.com/biz/mchip the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products connecting to the microchip bbs connect worldwide to the microchip bbs using either the internet or the compuserve ? communications net- work. internet: you can telnet or ftp to the microchip bbs at the address: mchipbbs.microchip.com compuserve communications network: when using the bbs via the compuserve network, in most cases, a local call is your only expense. the microchip bbs connection does not use compuserve membership services, therefore you do not need compuserve membership to join microchip's bbs. there is no charge for connecting to the microchip bbs. the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allow multiple users various baud rates depending on the local point of access. the following connect procedure applies in most loca- tions. 1. set your modem to 8-bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress the key and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress the key and ?host name:? will appear. 5. type mchipbbs, depress the key and you will be connected to the microchip bbs. in the united states, to find the compuserve phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with ?host name:?, type network, depress the key and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 723-1550 for your local compuserve number. microchip regularly uses the microchip bbs to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for microchip systems software products. for each sig, a moderator monitors, scans, and approves or disap- proves files submitted to the sig. no executable files are accepted from the user community in general to limit the spread of computer viruses.
pic16c84 ds30445d-page 11-106 ? 1996-2013 microchip technology inc. reader response it is our intention to provide you with the best documentati on possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clar ity, subject matter, and ways in which our documentation can better serve you, please fax your comments to t he technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30445d pic16c84
pic16c84 ? 1996-2013 microchip technology inc. ds30445d-page 107 pic16c84 product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office. sales and support part no. -xx x /xx xxx pattern package temperature range frequency range device device pic16c84 (2) , PIC16C84T (3) pic16lc84 (2) , pic16lc84t (3) frequency range 04 10 = 4 mhz = 10 mhz temperature range b (1) i =0 ? c to +70 ? c (commercial) =-40 ? c to +85 ? c (industrial) package p so = pdip = soic (gull wing, 300 mil body) pattern 3-digit pattern code for qtp, rom (blank otherwise) examples: a) pic16c84 -04/p 301 = commercial temp., pdip package, 4mhz, normal v dd limitis, qtp pattern #301. b) pic16lc84 - 04i/so = industrial temp., soic package, 200khz, extended v dd limits. note 1: b = blank 2: c = standard v dd range lc = extended v dd range 3: t = in tape and reel - soic, ssop packages only. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists fo r a particular device, please contact one of the following: 1. your local microchip sales office (see last page) 2. the microchip?s bulletin board, via your local com puserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using.
pic16c84 ds30445d-page 108 ? 1996-2013 microchip technology inc.
? 1996-2013 microchip technology inc. ds30445d-page 109 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1996-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769256 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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